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? semiconductor components industries, llc, 2006 april, 2006 ? rev. 16 1 publication order number: NCV4299/d NCV4299 150 ma low?dropout voltage regulator the NCV4299 is a family of precision micropower voltage regulators with an output current capability of 150 ma. it is available in 5.0 v or 3.3 v output voltage, and is housed in an 8?lead son and in a 14?lead son (fused) package. the output voltage is accurate within 2% with a maximum dropout voltage of 0.5 v at 100 ma. low quiescent current is a feature drawing only 90 a with a 1 ma load. this part is ideal for any and all battery operated microprocessor equipment. the device features microproce ssor interfaces including an adjustable reset output and adjustable system monitor to provide shutdown early warning. an inhibit function is available on the 14?lead part. with inhibit active, the regulator turns off and the device consumes less than 1.0 a of quiescent current. the part can withstand load dump transients making it suitable for use in automotive environments. features ? 5.0 v, 3.3 v 2%, 150 ma ? extremely low current consumption ? 90 a (typ) in the on mode ? 1.0 a in the off mode ? early warning ? reset output low down to v q = 1.0 v ? adjustable reset threshold ? wide temperature range ? fault protection ? 60 v peak transient voltage ? ?40 v reverse voltage ? short circuit ? thermal overload ? internally fused leads in the so?14 package ? inhibit function with a current consumption in the off mode ? ncv prefix for automotive and other applications requiring site and change control ? pb?free packages are available so?14 d suffix case 751a pin connections so ro q inh gnd gnd gnd gnd 114 gnd gnd i d si radj marking diagrams xx = 33 (3.3 v version) = 50 (5.0 v version) a = assembly location l, wl = wafer lot y = year w, ww = work week g = pb?free package = pb?free package (note: microdot may be in either location) gnd d 18 ro radj so si q i so?8 d suffix case 751 1 8 http://onsemi.com NCV4299g awlyww 1 14 1 14 4299 alyw 1 8 see detailed ordering and shipping information in the package dimensions section on page 21 of this data sheet. ordering information v4299xxg awlyww 1 14
NCV4299 http://onsemi.com 2 figure 1. so?8 simplified block diagram i bandgap reference + ? ? + 1.36 v si radj + ? + current limit and saturation sense + ? 1.85 v 8 a ro so d gnd q r so r ro pin function description ? so?8 package pin symbol description 1 i input. battery supply input voltage. bypass directly to gnd with ceramic capacitor. 2 si sense input. can provide an early warning signal of an impending reset condition when used with so. connect to q if not used. 3 radj reset adjust. use resistor divider to q to adjust reset threshold lower. connect to gnd if not used. 4 d reset delay. connect external capacitor to ground to set delay time. 5 gnd ground. 6 ro reset output. npn collector output with internal 20 k pullup to q. notifies user of out of regulation condi- tion. leave open if not used. 7 so sense output. npn collector output with internal 20 k pullup to q. can be used to provide early warning of an impending reset condition. leave open if not used. 8 q 5.0 v, 3.3 v, 2%, 150 ma output. use 22 f, e s r 5.0 to ground.
NCV4299 http://onsemi.com 3 figure 2. so?14 simplified block diagram i bandgap reference inh + ? ? + 1.36 v si radj + ? + current limit and saturation sense + ? 1.85 v 8 a ro so d gnd q r ro r so pin function description ? so?14 package pin symbol description 1 radj reset adjust. use resistor divider to q to adjust reset threshold lower. connect to gnd if not used. 2 d reset delay. connect external capacitor to ground to set delay time. 3 gnd ground. 4 gnd ground. 5 gnd ground. 6 inh inhibit. connect to i if not needed. a high turns the regulator on. 7 ro reset output. npn collector output with internal 20 k pullup to q. notifies user of out of regulation condi- tion. 8 so sense output. npn collector output with internal 20 k pullup to q. can be used to provide early warning of an impending reset condition. 9 q 5.0 v, 3.3 v, 2%, 150 ma output. use 22 f, e s r 5.0 to ground. 10 gnd ground. 11 gnd ground. 12 gnd ground. 13 i input. battery supply input voltage. 14 si sense input. can provide an early warning signal of an impending reset condition when used with so.
NCV4299 http://onsemi.com 4 maximum ratings rating symbol min max unit input voltage to regulator (dc) v i ?40 45 v input peak transient voltage to regulator wrt gnd ? ? 60 v inhibit (inh ) (note 1) v inh ?40 45 v sense input (si) v si ?0.3 45 v sense input (si) i si ?1.0 1.0 ma reset threshold (radj) v re ?0.3 7.0 v reset threshold (radj) i re ?10 10 ma reset delay (d) v d ?0.3 7.0 v reset output (ro) v ro ?0.3 7.0 v sense output (so) v so ?0.3 7.0 v output (q) v q ?0.3 16 v output (q) i q ?5.0 ? ma esd capability, human body model (note 5) esd hb 2.0 ? kv esd capability, machine model (note 5) esd mm 200 ? v esd capability, charged device model (note 5) esd cdm 1.0 ? kv junction temperature t j ? 150 c storage temperature t stg ?50 150 c operating range input voltage 5.0 v version 3.3 v version v i 4.5 4.4 45 45 v junction temperature t j ?40 150 c lead temperature soldering reflow (note 3) lead temperature soldering (note 5) reflow (smd styles only), leaded 60?150 sec above 183, 30 sec max at peak t sld ? 240 pk c reflow (smd styles only), lead free 60s?150 sec above 217, 40 sec max at peak t sld ? 265 pk c moisture sensitivity level msl level 1 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. 14 pin package only. 2. preliminary numbers. 3. per ipc / jedec j?std?020c. 4. measured to pin 4. all ground pins connected to ground. 5. this device series incorporates esd protection and is tested by the following methods: esd hbm tested per aec?q100?002 (eia/jesd22?a114) esd mm tested per aec?q100?003 (eia/jesd22?a115) esd cdm tested per eia/jes d22/c101, field induced charge model.
NCV4299 http://onsemi.com 5 thermal characteristics characteristic test conditions (typical value) unit note 6 note 7 note 8 so?8 junction?to?tab ( jlx , jlx ) junction?to?ambient (r ja , ja ) 54 172 52 144 48 118 c/w so?14 junction?to?tab ( jlx , jlx ) junction?to?ambient (r ja , ja ) 19 112 21 89 20 67 c/w 6. 2 oz copper, 50 mm sq copper area, 1.5 mm thick fr4 7. 2 oz copper, 150 mm sq copper area, 1.5 mm thick fr4 8. 2 oz copper, 500 mm sq copper area, 1.5 mm thick fr4 electrical characteristics (?40 c < t j < 150 c; v i = 13.5 v unless otherwise noted.) characteristic symbol test conditions min typ max unit output q output voltage (5.0 v version) v q 1.0 ma < i q < 150 ma, 6.0 v < v i < 16 v 4.9 5.0 5.1 v output voltage (3.3 v version) v q 1.0 ma < i q < 150 ma, 5.5 v < v i < 16 v 3.23 3.3 3.37 v current limit i q ? 250 400 500 ma quiescent current (i q = i i ? i q ) i q inh on, i q < 1.0 ma, t j = 25 c ? 86 100 a quiescent current (i q = i i ? i q ) i q inh on, i q < 1.0 ma ? 90 105 a quiescent current (i q = i i ? i q ) i q inh on, i q = 10 ma ? 170 500 a quiescent current (i q = i i ? i q ) i q inh on, i q = 50 ma ? 0.7 2.0 ma quiescent current (i q = i i ? i q ) i q inh = 0 v, t j = 25 c ? ? 1.0 a dropout voltage (note 9) v dr i q = 100 ma ? 0.22 0.50 v load regulation v q i q = 1.0 ma to 100 ma ? 5.0 30 mv line regulation v q v i = 6.0 v to 28 v, i q = 1.0 ma ? 10 25 mv power supply ripple rejection p srr ?r = 100 hz, vr = 1.0 vpp, i q = 100 ma ? 66 ? db inhibit (inh ) (14 pin package only) inhibit off voltage v inhoff v q < 1.0 v ? ? 0.8 v inhibit on voltage 5.0 v version 3.3 v version v inhon v q > 4.85 v v q > 3.2 v 3.5 3.5 ? ? ? ? v input current i inh on i inh off inh on inh = 0 v ? ? 3.0 0.5 10 2.0 a reset (ro) switching threshold 5.0 v version 3.3 v version v rt ? 4.50 2.96 4.60 3.06 4.80 3.16 v output resistance r ro ? 10 20 40 k reset output low voltage 5.0 v version 3.3 v version v ro q < 4.5 v, internal r ro , i ro = ?1.0 ma q < 2.96 v, internal r ro , i ro = ?1.0 ma ? ? 0.17 0.17 0.40 0.40 v allowable external reset pullup resistor v roext external resistor to q 5.6 ? ? k delay upper threshold v ud ? 1.5 1.85 2.2 v delay lower threshold v ld ? 0.4 0.5 0.6 v 9. measured when the output voltage v q has dropped 100 mv from the nominal value obtained at v i = 13.5 v.
NCV4299 http://onsemi.com 6 electrical characteristics (continued) (?40 c < t j < 150 c; v i = 13.5 v unless otherwise noted.) characteristic symbol test conditions min typ max unit reset (ro) delay output low voltage 5.0 v version 3.3 v version v d q < 4.5 v, internal r ro q < 2.96 v, internal r ro ? ? ? 0.017 0.1 0.1 v delay charge current 5.0 v version 3.3 v version i d q < 4.5 v, internal r ro , v d = 1.0 v q < 2.96 v, internal r ro , v d = 1.0 v 4.0 ? 7.1 ? 12 ? a power on reset delay time t d c d = 100 nf 17 28 35 ms reset reaction time t rr c d = 100 nf 0.5 2.2 4.0 s reset adjust switching threshold 5.0 v version 3.3 v version v radj,th q > 3.5 v q > 2.3 v 1.26 ? 1.36 ? 1.44 ? v input voltage sense (si and so) sense input threshold high v si,high ? 1.34 1.45 1.54 v sense input threshold low v si,low ? 1.26 1.36 1.44 v sense input hysteresis ? (sense threshold high) ? (sense threshold low) 50 90 130 mv sense input current i si ? ?1.0 0.1 1.0 a sense output resistance r so ? 10 20 40 k sense output low voltage v so v si < 1.20 v, v i > 4.2 v, i so = 0 a ? 0.1 0.4 v allowable external sense out pullup resistor r soext ? 5.6 ? ? k si high to so high reaction time t pdsolh ? ? 4.4 8.0 s si low to so low reaction time t pdsohl ? ? 3.8 5.0 s NCV4299 i inh d radj si q ro so gnd i i i inh (14?pin part only) i d i d c d 100 nf i radj i si v radj v si v inh v i i q v q v ro v so i q figure 3. measurement circuit
NCV4299 http://onsemi.com 7 typical performance characteristics ? 5.0 v option figure 4. output voltage vq vs. temperature tj figure 5. output voltage vq vs. input voltage figure 6. charge current ld, c vs. temperature tj figure 7. drop voltage vdr vs. output current iq figure 8. switching voltage vud and vld vs. temperature tj 5 2 1 0 010 output voltage, vq volts input voltage, vi volts 4 3 5 r l = 50 6 1 5 figure 9. reset adjust switching threshold vradjth vs. temperature tj 4.9 ?40 80 vq volts temperature c 5.0 ?20 60 100 40 20 120 v i = 13.5 v r l = 1 k 5.1 160 0 140 500 200 100 0 0 100 drop voltage, vdr, mv output current iq, ma 400 300 50 ?40 c 25 c 150 125 c 6.0 ?40 80 charge current, a temperature c 7.0 ?20 60 100 40 20 120 v i = 13.5 v v d = 1 v r l = 5 k 8.0 160 0 140 0.0 ?40 80 switching voltage, v temperature, c 1.6 40 120 3.2 160 0 2.8 2.4 2.0 0.4 1.2 0.8 0.9 ?40 80 vradjth, v temperature tj, c 1.3 40 120 16 0 0 1.5 1.4 1.0 1.2 1.1 v ld, v i = 13.5v v ud
NCV4299 http://onsemi.com 8 figure 10. sense threshold vsi vs. temperature tj figure 11. output current limit iq vs. input voltage, vi figure 12. current consumption iq vs. output current iq figure 13. current consumption iq vs. output current iq figure 14. rro, rso resistance vs. temperature figure 15. current consumption iq vs. input voltage vi ?40 80 vsi, v temperature, c 1.3 40 120 vsiu 160 0 1.5 1.4 1.0 1.2 1.1 1.6 030 output current iq, ma input voltage, vi, v 200 20 4 0 t j = 25 c 10 300 250 50 150 100 350 0 output current iq, ma 2.0 20 40 10 0.5 1.5 1.0 0.0 030 current consumption iq, ma 50 60 output current iq, ma 8.0 80 16 0 40 2.0 6.0 4.0 0.0 0 120 current consumption iq, ma temperature c 80 160 40 20 40 30 10 0 120 rro, rso resistance, ohms ?40 v i = 13.5v r l = 5 k input voltage vi, v 16.0 20 4 0 10 2.0 14.0 4.0 0.0 030 current consumption iq, ma 12.0 10.0 8.0 6.0 vsil r l 200 r l 100 r l 50 r l 33 t j = 125 c v q = 0 v
NCV4299 http://onsemi.com 9 figure 16. current consumption iq vs. input voltage vi figure 17. current consumption iq vs. input voltage vi figure 18. stability vs. output capacitor esr 90 70 65 60 618 current consumption iq, a input voltage vi, v 80 81620 14 75 85 12 22 iq 100 a 24 10 26 6 2 1 0 618 current consumption iq, ma input voltage vi, v 4 81620 14 3 5 12 22 24 10 26 0 80 output capacitor esr, ohms output current, ma 5 60 100 40 20 120 45 160 0 140 10 15 20 25 30 35 40 iq 10ma iq 50ma iq 100ma unstable region stable region 1 f to 100 f 0.1 f unstable region 0.1 f only v i = 13.5v t a = 25 c
NCV4299 http://onsemi.com 10 typical performance characteristics ? 3.3 v option figure 19. current consumption vs. junction temperature figure 20. current consumption vs. output current t j , junction temperature ( c) i q , output current (ma) 100 80 60 40 20 0 ?20 ?40 0.1 1 10 100 1000 140 120 100 80 60 40 20 0 0 2 4 6 8 10 12 figure 21. current consumption vs. input voltage figure 22. output voltage vs. junction temperature v i , input voltage (v) t j , junction temperature ( c) 50 40 30 20 10 0 0 1 2 3 4 5 160 120 80 40 0 ?40 2.9 3.0 3.1 3.2 3.3 3.4 3.5 figure 23. reverse output current vs. output voltage figure 24. maximum output current vs. input voltage v q , output voltage (v) v i , input voltage (v) 50 40 30 20 10 0 ?300 ?250 ?200 ?150 ?100 ?50 0 50 0 0 50 100 150 200 250 300 350 i q , current consumption ( a) 140 120 i q , current consumption (ma) 180 160 v q , output voltage (v) i q , current consumption (ma) v i = 13.5 v i q = 1 ma t j = 150 c t j = 25 c t j = ?40 c t j = 25 c r l = 33 r l = 50 r l = 100 200 i q , reverse output current (ma) i q , maximum output current (ma) v i = 0 v t j = 125 c t j = 25 c t j = ?40 c t j = 125 c t j = 25 c v q = 0 v 25 v i = 13.5v r l = 1 k
NCV4299 http://onsemi.com 11 figure 25. output voltage at input voltage extremes figure 26. 3.3 v output stability with output capacitor esr v i , input voltage (v) i q , output current (ma) 3 2 1 0 0 1 2 5 6 130 100 70 40 10 0 0.01 0.1 1 10 100 1000 figure 27. 3.3 v output stability with output capacitor esr figure 28. inhibit input current at input voltage extremes v i , input voltage (v) 40 30 20 10 0 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0.01 0.02 figure 29. inhibit input current at inhibit input voltage extremes figure 30. reset trigger threshold vs. junction temperature v inh , inhibit input voltage (v) t j , junction temperature ( c) 40 30 20 10 0 0 1 2 3 4 5 6 140 0 2.95 3.00 3.05 3.10 3.15 3.20 3.25 v q , output voltage (v) 5 4 output capacitor esr ( ) i inh , inhibit input current ( a) stable region max esr for v in = 6 v c q = 22 f t j = 150 c i inh , inhibit input current ( a) v rt , reset trigger threshold (v) t j = ?40 c t j = 25 c t j = 125 c reset v i = 13.5 v 3 4 t j = 25 c r l = 50 max esr for v in = 25 v i q , output current (ma) 130 100 70 40 10 0 0.01 0.1 1 10 100 output capacitor esr ( ) stable region max esr for v in = 6 v c q = 22 f t j = ?40 c max esr for v in = 25 v 0 t j = 150 c t j = 25 c t j = ?40 c t j = 125 c inh = off 1000 ?20 ?40 60 40 20 120 100 80
NCV4299 http://onsemi.com 12 figure 31. reset delay time vs. junction temperature figure 32. sense threshold vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 20 0 ?20 ?40 10 15 20 35 100 40 20 0 ?20 ?40 1.30 1.35 1.40 1.45 1.50 figure 33. delay capacitor charge current vs. junction temperature figure 34. drop voltage vs. output current i q , output current (ma) 160 120 80 40 0 1.05 1.06 1.07 1.08 1.09 1.14 1.15 figure 35. switching voltage v ud and v ld vs. junction temperature figure 36. reset adjust switching threshold vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 120 80 40 0 ?40 0 0.5 1.0 3.0 160 0 0.9 1.0 1.1 1.2 1.3 1.4 1.5 t rd , reset delay time (ms) 140 40 v si , sense threshold (v) v dr , drop voltage (v) v ud , v ld , switching voltage (v) v radj,th (v) v ud v i = 13.5 v 25 30 v i = 13.5 v c d = 100 nf t j , junction temperature ( c) 140 120 80 40 0 ?40 0 3 4 5 8 i ch , delay capacitor charge current ( a) v i = 13.5 v v d = 1 v 1.10 t j = 25 c t j = ?40 c t j = 125 c v dr = v imin ? v q 100 80 60 120 80 60 120 140 v i = 13.5 v v si high v si low 7 6 1 2 100 60 20 ?20 1.11 1.12 1.13 ?40 80 40 120 v ld 1.5 2.0 2.5 160
NCV4299 http://onsemi.com 13 figure 37. current consumption vs. input voltage figure 38. r ro , r so resistance vs. junction temperature v i , input voltage (v) t j , junction temperature ( c) 30 20 10 0 0 0.5 1.5 160 120 80 40 0 ?40 10 15 20 25 35 40 i q , current consumption (ma) 40 r ro , r so resistance (k ) 1.0 t j = 25 c i q = 10 ma i q = 1 ma 30
NCV4299 http://onsemi.com 14 application description NCV4299 the NCV4299 is a family of precision micropower voltage regulators with an output current capability of 150 ma at 5.0 v and 3.3 v. the output voltage is accurate within 2% with a maximum dropout voltage of 0.5 v at 100 ma. low quiescent current is a feature drawing only 90 a with a 100 a load. this part is ideal for any and all battery operated microprocessor equipment. microprocessor control logic includes an active reset output ro (with delay), and a si/so monitor which can be used to provide an early warning signal to the microprocessor of a potential impending reset signal. the use of the si/so monitor allows the microprocessor to finish any signal processing before the reset shuts the microprocessor down. internal output resistors on the ro and so pins pulling up to the output pin q reduce external component count. an inhibit function is available on the 14?lead part. with inhibit active, the regulator turns off and the device consumes less that 1.0 a of quiescent current. the active reset circuit operates correctly at an output voltage as low as 1.0 v. the reset function is activated during the powerup sequence or during normal operation if the output voltage drops outside the regulation limits. the reset threshold voltage can be decreased by the connection of an external resistor divider to the radj lead. the regulator is protected against reverse battery, short circuit, and thermal overload conditions. the device can withstand load dump transients making it suitable for use in automotive environments. NCV4299 circuit description the low dropout regulator in the NCV4299 uses a pnp pass transistor to give the lowest possible dropout voltage capability. the current is internally monitored to prevent oversaturation of the device and to limit current during over current conditions. additional circuitry is provided to protect the device during overtemperature operation. the regulator provides an output regulated to 2%. other features of the regulator include an undervoltage reset function and a sense circuit. the reset function has an adjustable time delay and an adjustable threshold level. the sense circuit trip level is adjustable and can be used as an early warning signal to the controller. an inhibit function that turns off the regulator and reduces the current consumption to less than 1.0 a is a feature available in the 14 pin package. output regulator the output is controlled by a precision trimmed reference. the pnp output has saturation control for regulation while the input voltage is low, preventing oversaturation. current limit and voltage monitors complement the regulator design to give safe operating signals to the processor and control circuits. stability considerations the input capacitor c i is necessary for compensating input line reactance. possible oscillations caused by input inductance and input capacitance can be damped by using a resistor of approximately 1.0 in series with c i . the output or compensation capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero esr can cause instability. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (?25 c to ?40 c), both the value and esr of the capacitor will vary considerably. the capacitor manufacturer?s data sheet usually provides this information. the value for the output capacitor c q shown in figures 39 and 40 should work for most applications, however, it is not necessarily the optimized solution. stability is guaranteed at values c q 22 f and an esr 5.0 within the operating temperature range. actual limits are shown in a graph in the typical performance characteristics section.
NCV4299 http://onsemi.com 15 NCV4299 i d so q si ro gnd v bat figure 39. test and application circuit showing all compensation and sense elements for the 8 pin package part 0.1 f c i * c d r radj1 r radj2 r s11 r s12 c q ** 22 f v dd microprocessor i/o i/o *c i required if regulator is located far from the power supply filter. **c q required for stability. cap must operate at minimum temperature expected. radj NCV4299 i d so q si ro gnd v bat figure 40. test and application circuit showing all compensation and sense elements for the 14 pin package part with inhibit function 0.1 f c i * c d r radj1 r radj2 r s11 r s12 c q ** 22 f v dd microprocessor i/o i/o *c i required if regulator is located far from the power supply filter. **c q required for stability. cap must operate at minimum temperature expected. radj inh inh
NCV4299 http://onsemi.com 16 reset output (ro) a reset signal, reset output (ro, low voltage) is generated as the ic powers up. after the output voltage v q increases above the reset threshold voltage v rt , the delay timer d is started. when the voltage on the delay timer v d passes v ud , the reset signal ro goes high. a discharge of the delay timer (v d ) is started when v q drops and stays below the reset threshold voltage v rt . when the voltage of the delay timer (v d ) drops below the lower threshold voltage v ld , the reset output voltage v ro is brought low to reset the processor. the reset output ro is an open collector npn transistor, controlled by a low voltage detection circuit. the circuit is functionally independent of the rest of the ic, thereby guaranteeing that ro is valid for v q as low as 1.0 v. v i v q v d v ro v rt v ud v ld v ro , sat t d t rr < t rr t t t t dv dt i d c d power?on?reset thermal shutdown voltage dip at input undervoltage secondary spike overload at output figure 41. reset timing diagram reset adjust (radj) the reset threshold v rt can be decreased from a typical value of 4.65 v to as low as 3.5 v by using an external voltage divider connected from the q lead to the pin radj, as shown in figures 39 and 40. the resistor divider keeps the voltage above the v radj,th , (typ. 1.35 v), for the desired input voltages and overrides the internal threshold detector. adjust the voltage divider according to the following relationship: v thres v radj, th (r adj1 r adj2 ) r adj2 (eq. 1) if the reset adjust option is not needed, the radj?pin should be connected to gnd causing the reset threshold to go to its default value (typ. 4.65 v). reset delay (d) the reset delay circuit provides a delay (programmable by capacitor c d ) on the reset output ro lead. the delay lead d provides charge current i d (typically 8.0 ma) to the external delay capacitor c d during the following times: 1. during powerup (once the regulation threshold has been exceeded). 2. after a reset event has occurred and the device is back in regulation. the delay capacitor is set to discharge when the regulation (v rt , reset threshold voltage) has been violated. when the delay capacitor discharges to down to v ld , the reset signal ro pulls low.
NCV4299 http://onsemi.com 17 setting the delay time the delay time is set by the delay capacitor c d and the charge current i d . the time is measured by the delay capacitor voltage char ging from the low level of v d,sat to the higher level v ud . the time delay follows the equation: t d [c d (v ud ?v d, sat )] i d (eq. 2) example: using c d = 100 nf. use the typical value for v d,sat = 0.1 v. use the typical value for v ud = 1.8 v. use the typical value for delay charge current i d = 6.5 a. t d [100 nf(1.8?0.1 v)] 6.5 a 26.2 ms (eq. 3) when the output voltage v q drops below the reset threshold voltage v rt , the voltage on the delay capacitor v d starts to drop. the time it takes to drop below the lower threshold voltage of v ld is the reset reaction time, t rr . this time is typically 1.0 s for a delay capacitor of 0.1 f. the reset reaction time can be estimated from the following relationship: t rr 10 ns nf c d (eq. 4) sense input (si)/sense output (so) voltage monitor an on?chip comparator is available to provide early warning to the microprocessor of a possible reset signal. the reset signal typically turns the microprocessor off instantaneously. this can cause unpredictable results with the microprocessor. the signal received from the so pin will allow the microprocessor time to complete its present task before shutting down. this function is performed by a comparator referenced to the band gap voltage. the actual trip point can be programmed externally using a resistor divider to the input monitor (si) (figures 39 and 40). the typical threshold is 1.35 v on the si pin. signal output figure 42 shows the so monitor waveforms as a result of the circuits depicted in figur es 39 and 40. as the output voltage v q falls, the monitor threshold v si,low is crossed. this causes the voltage on the so output to go low sending a warning signal to the microprocessor that a reset signal may occur in a short period of time. t wa r n i n g is the time the microprocessor has to complete the function it is currently working on and get ready for the reset shutdown signal. t pd so lh t pd so h l t t sense input voltage v sl, high v sl, low sense output high low v q s i v si,low v ro s o t warning figure 42. so warning timing waveform figure 43. sense timing diagram calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator is: p d(max) [v i(max) ?v q(min) ]i q(max) v i(max) iq (eq. 5) where: v i(max) is the maximum input voltage, v q(min) is the minimum output voltage, i q(max) is the maximum output current for the application, and i q is the quiescent current the regulator consumes at i q(max) . once the value of p d(max) is known, the maximum permissible value of r ja can be calculated: r ja (150 c?t a ) p d (eq. 6) the value of r ja can then be compared with those in the package section of the data sheet. those packages with r ja ?s less than the calculated value in equation 6 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required.
NCV4299 http://onsemi.com 18 heatsinks a heatsink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja : r ja r jc r cs r sa (eq. 7) where: r jc = the junction?to?case thermal resistance, r cs = the case?to?heatsink thermal resistance, and r sa = the heatsink?to?ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it too is a function of package type. r cs and r sa are functions of the package type, heatsink and the interface between them. these values appear in heatsink data sheets of heatsink manufacturers. thermal, mounting, and heatsinking are discussed in the on semiconductor application note an1040/d, available on the on semiconductor website.
NCV4299 http://onsemi.com 19 soic 8 lead 10% 10% 5% 2% 20% 1% 50% duty cycle psi la (soic?8) single pulse (soic?8) cu area = 10 mm 2 , 1.0 oz figure 44. transient thermal response simulation to a single pulse 1 oz (log?log) 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 100 0 time (sec) r(t) ( c/w) 1000 100 10 1 0.1 figure 45. transient thermal response simulation to a single pulse with duty cycles applied (log?log) (pcb = 50 mm 2 1 oz) 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 100 0 pulse time (sec) r(t) ( c/w) 1000 100 10 1 0.001 0.1 0.01 figure 46. transient thermal response simulation to a single pulse with duty cycles applied (log?log) (pcb = 250 mm 2 1 oz) 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 100 0 pulse time (sec) r(t) ( c/w) 1000 100 10 1 0.001 0.1 0.01 25 mm 2 , 1.0 oz 100 mm 2 , 1.0 oz 250 mm 2 , 1.0 oz 500 mm 2 , 1.0 oz 5% 2% 20% 1% 50% duty cycle psi la (soic?8) single pulse (soic?8)
NCV4299 http://onsemi.com 20 soic 14 lead 10% 10% 5% 2% 20% 1% 50% duty cycle psi la (soic?14) single pulse (soic?14) cu area = 10 mm 2 , 1.0 oz figure 47. transient thermal response simulation to a single pulse 1 oz (log?log) 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 100 0 time (sec) r(t) ( c/w) 1000 100 10 1 0.1 figure 48. transient thermal response simulation to a single pulse with duty cycles applied (log?log) (pcb = 50 mm 2 1 oz) 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 100 0 pulse time (sec) r(t) ( c/w) 1000 100 10 1 0.001 0.1 0.01 figure 49. transient thermal response simulation to a single pulse with duty cycles applied (log?log) (pcb = 250 mm 2 1 oz) 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 100 0 pulse time (sec) r(t) ( c/w) 100 10 1 0.001 0.1 0.01 25 mm 2 , 1.0 oz 100 mm 2 , 1.0 oz 250 mm 2 , 1.0 oz 500 mm 2 , 1.0 oz 5% 2% 20% 1% 50% duty cycle psi la (soic?14) single pulse (soic?14)
NCV4299 http://onsemi.com 21 ordering information device package shipping ? NCV4299d1 so?8 98 units/rail NCV4299d1g so?8 (pb?free) 98 units/rail NCV4299d1r2 so?8 2500 tape & reel NCV4299d1r2g so?8 (pb?free) 2500 tape & reel NCV4299d2 so?14 55 units/rail NCV4299d2g so?14 (pb?free) 55 units/rail NCV4299d2r2 so?14 2500 tape & reel NCV4299d2r2g so?14 (pb?free) 2500 tape & reel NCV4299d233g so?14 (pb?free) 55 units/rail NCV4299d233r2g so?14 (pb?free) 2500 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NCV4299 http://onsemi.com 22 package dimensions soic?8 nb case 751?07 issue ah seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155
mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
NCV4299 http://onsemi.com 23 package dimensions so?14 d suffix case 751a?03 issue g notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. ?a? ?b? g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t ?t? f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 NCV4299/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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